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Coherent cache
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#	Item
11	103 A Coherent Distributed File Cache With Directory Write-behind Add to Reading List Source URL: tim-mann.org Language: English - Date: 2006-11-21 14:57:44 Network file systems Cache CPU cache Consistency model File system Representational state transfer Computing Computer hardware Computer architecture
12	HIERARCHICAL DIRECTORY CONTROLLERS IN THE NUMACHINE MULTIPROCESSOR by Alexander Grbic Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:44 Cache coherency CPU cache Cache Dynamic random-access memory Memory hierarchy Controller Bus sniffing Scalable Coherent Interface Computing Computer hardware Computer memory
13	The NUMAchine Multiprocessor: Design and Analysis Robin Grindley A thesis submitted in conformity with the requirements Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-11-29 17:16:53 Central processing unit Parallel computing Computer memory Concurrent computing CPU cache Scalable Coherent Interface Non-Uniform Memory Access Cache coherence Microarchitecture Computing Computer hardware Computer architecture
14	The NUMAchine Multiprocessor R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vra Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 2000-09-02 04:07:38 CPU cache Non-Uniform Memory Access Cache coherence Speedup Cache-only memory architecture SMP - Symmetric Multiprocessor System Cache Memory hierarchy Scalable Coherent Interface Computing Parallel computing Computer memory
15	NUMAchine Principles of Operation for System Programmers ** THIS IS A PRELIMINARY DOCUMENT. It is continually evolving and is subject to change at any time. Steve Caranci Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:53** Computer memory CPU cache Conventional PCI Cache Dynamic random-access memory Interrupt Scalable Coherent Interface Direct memory access Computer hardware Computing Computer architecture
16	Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:24:25 Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing
17	W h i t e P a p e r Performance and Productivity Breakthroughs with Very Large Coherent Add to Reading List Source URL: www.sgi.com Language: English - Date: 2012-02-16 16:29:35 Distributed computing architecture Supercomputers Computer memory Computer buses NUMAlink Distributed memory InfiniBand CPU cache Shared memory Computing Concurrent computing Parallel computing
18	Tech. Rep[removed]Using Simple Page Placement Policies to Reduce the Cost of Cache Fills in Coherent Shared-Memory Systems Michael Marchetti, Leonidas Kontothanassis, Ricardo Bianchini, and Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 21:03:45 Parallel computing Central processing unit Computer memory Cache CPU cache Non-Uniform Memory Access Shared memory Page Translation lookaside buffer Computing Concurrent computing Computer hardware
19	Formal Analysis of the ACE Specification for Cache Coherent Systems-On-Chip Abderahman KRIOUILE PhD student, STMicroelectronics – Inria Rhône-Alpes – LIG Add to Reading List Source URL: lvl.info.ucl.ac.be Language: English - Date: 2013-10-02 08:13:33 Computer memory Parallel computing Cache coherence Concurrent computing CPU cache Cache Computing Cache coherency Computer hardware
20	MIPS32® 1004K™ Coherent Processing System (CPS) MIPS32 1004K™ ® multiprocessor IP Add to Reading List Source URL: www.imgtec.com Language: English - Date: 2013-07-17 06:19:48 Microprocessors Instruction set architectures Computer memory MIPS Technologies MIPS architecture CPU cache Multi-core processor Cache Loongson Computer architecture Computing Computer hardware

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